Yet Another Text About the Introduction to the 6502 Microprocessor
By Joseph Norman AKA Devster-999
- Address Modes
- Interfacing - Coming soon!
- Update History
Right to the point, the 6502 has sixteen address lines and an 8-bit bidirectional data bus. The 6502 has a minimal number of control lines (outputs), which are as follows:
- θ0 - Phrase 1 clock
- θ2 - Phrase 2 clock
- R/W - Read, Write
- SYNC - Indicates opcode fetch cycle
Inputs are as follows:
- θ/0 - Crystal oscillator input
- RES - Reset
- RDY - Ready
- IRQ - Interrupt request
- S.O. - Set Overflow
Pinouts of the 6502:
There are no general purpose registers built into the 6502. The 6502 has 6 built in, 8-bit registers, all which can be directly involved with an instruction. All arithmetic and logic operations are carried out using the accumulator (A) and a memory location. The registers are:
- Y - Index Y
- X - Index X
- S - Stack Pointer
- A - Accumulator
- PCL - Porgram counter low
- PCH - Program counter high
|Absolute Indexed, X
|Absolute Indexed, Y
|Zero Page Indexed, X
|Zero Page Indexed, Y
aa OR aaaa
"a" stands for the 4-bit absolute address digit, and "d" represents a 4-bit immediate value
- In this mode, the operand itself is contained in the instruction. It is called the immediate mode because the data is found immediately following the opcode. It is either the second byte of the instruction with an 8-bit operand. The use of the # sign specifies the immediate mode, which seems to be a universal method.
- The address of the operand appears in the instruction itself when the absolute mode is used. The instruction must contain three bytes for the absolute mode: the first for the opcade and the second and third for the address. The low byte appears at the lower of the two addresses. Because a 16-bit address is specified in the operand, the assembler knows to use the absolute mode.
Zero Page Mode
- For the 6502, when a high byte of the address equals 0, page zero is being addressed. Page zero has special meaning for the 6502. It usually contains small buffers or memory registers. A special mode of addressing, called zero page addressing, allows 8-bit memory addresses for page zero. Therefore, 2-byte instructions are used for zero page addressing. Memory-mapped I/O is used for the 6502. There is no seperate line to indicate that the I/O segment is being addressed. It is possible to implement the I/O ports on page zero.
- This mode is identicle to the absolute mode except that the operand is in page zero. The assembler recognizes that the zero page mode is to be used because the address can be equated to an 8-bit number. Using this mode makes more eficient use of memory because only one byte is required for the address.
- Some instructions specify the operand in the opcade. Therefore no other operand is specified. In these instructions the mode is implied by the opcode. Instructions that utilize this are like INY (INcrement the contents of Y) or SEC (SEt Carry flag).
Indirect Absolute Mode
- Only the jump (JMP) instruction uses the indirect absolute mode. As with the absolute mode, this is a three-byte instruction. The second and third bytes of the instruction (which uses JMP also uses) contains an address where the low byte of the destination address is contained. The next address contains the address of the high byte of the destination address. This mode allows the programmer to have a table of addresses. Jumps may then be executed through the table.
- Notice the use of the parens. They enclose an address, which means that this is not the address of the operand but its the address of the address of the operand. In this case, the operand is the destination of the jump. The use of the parens thends to be a universal method of specifying the indirect mode.
Absolute Indexed Mode
- This mode is used in conjunction with the X and Y registers. The effective address of the operand is determined by adding the contents of the index register to the address contained in the second and third byte of the instruction. This mode allows the programmer to create buffers where the index register contains the index or count value and the instruction contains the base address of the buffer. This is referred to as the "Absolute,X" or "Absolute,Y" modes.
Zero Page Indexed Mode
- The "Zero Page,X" and "Zero Page,Y" modes are the same as "Absolute,X" and "Absolute,Y" modes except that the operand appears on page zero. This is a two-byte instruction where the second byte is the base address and is indexed by either the Z or Y index registers to obtain the effective address. When the base and index are added, no carry is produced so that crossing of the page boundary does not occur. That is, page one is not entered.
Indexed Indirect Mode
- For this mode, only the X index register is used. The address of the opperand must be located in memory page zero, low byte first. The second byte of the two-byte instruction is indexed with the X index register to produce the address in page zero. Then the effective address of the operand is read from the two locations. Crossing of the zero page boundary cannot occur in this mode.
- Notice that in this mode parens are used to indicate the indirect or index indirect mode (aaX). In addition, the letter X is used with the address to indicate the index mode. It is useful to recognize that because the parens enclose the entire expression, indexing is performed first. Then, the result is the address of the operand.
Indirect Indexed Mode
- In this mode, the second byte of the instruction points to a location in page zero. The contents of this location is added to the contents of the Y index register. The result is the low order address of the effective address. The carry from this addition is added to the contents of the next location in memory page zero, which contains the high byte of the effective address.
- Because the parens enclose only the address (aa)Y, the indirect or index indirectt is performed first. Then the address thus obtained is indexed with the Y register.
- The relative mode of addressing is used only with branch instructions. Branch instructions are two-byte instructions. The first byte contains the opcode and the second byte contains the offset, or in other words, the relative address of the destination of the branch. When the processor has fetched the opcode and read the offset, the PC is pointing to the next address, which contains the next sequential instruction. The processor executes the branch by adding the offset to the PC. The result is that the PS now contains the effective destination address. The relative address is a signed 8-bit number. If the number is negative, the offset is negative - meaning that the branch will be backwards. The range of the offset is -128 to +127 bytes from the next address after the branch instruction.
- This mode is used when a one-byte instruction implies the use of the accumulator.
11/18/2003 - Document created